Programmable logic devices (PLDs) (e.g., field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), field programmable system on a chips (FPSCs), or other types of programmable devices) may be configured with various user designs to implement desired functionality. Typically, the user designs are synthesized and mapped into configurable resources (e.g., programmable logic gates, look-up tables (LUTs), embedded hardware, or other resources) and interconnections available in particular PLDs. Physical placement and routing for the synthesized and mapped user designs are then determined to generate configuration data for the particular PLDs.
Although the user design can be analyzed (e.g., tested) for compliance with timing requirements prior to routing, the results of such testing are merely estimates. In this regard, prior to routing, the precise signal paths between various components of the PLD are unknown. As a result, pre-routing timing estimates are often inaccurate, as the actual signal timing can be affected by the particular signal routing within the PLD.
However, if a timing error is detected after routing, one or more mapping, placement, and/or routing operations typically must be repeated to correct the error. All of these repeated operations can require significant processing time and resources.
Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.